There are well-known ways of testing for the proper operation of the functional elements of an integrated circuit. This is done by the imposition and/or determination at predefined instants of data values present at certain internal points of the integrated circuit. Such a technique of testing the internal paths of an integrated circuit, known as a scan path or an internal scan method, is described for example in “Enhancing Testability of LSI Circuits Via Test Points and Additional Logic, by M. Williams and J. Angel, IEEE Transactions on Computers, vol. C-22, No. 1, January 1973.
According to this technique, each of the latches of the logic circuit, whose state needs to be known and/or for which it is necessary to impose the content during the standard operation of the integrated circuit, is provided at its input with a multiplexer. The different latches and the multiplexers that are associated with these latches thus constitute an equivalent number of configurable cells whose access ports are individually controlled by the multiplexers.
The multiplexers of the different configurable cells are collectively controlled by an access controller or TAP (Test Access Port) controller which, depending on a control signal defining a chosen mode of operation, uses this set of configurable cells either as a standard functional circuit integrated into the logic circuit that it forms with the logic cells, or as a test circuit.
To do this, the TAP controller receives and/or addresses control signals on various control conductors by which it is connected to the different configurable cells. The control signals are, for example, a chaining control signal or a data propagation control signal. They authorize the modification and/or modify the paths of the circulation of data within the integrated circuit. This enables the capture of the data by the controller for their subsequent analysis.
In the standard mode of operation, the TAP controller therefore drives the multiplexers of the configurable cells in such a way that the latches of these cells are connected to surrounding logic cells to define one or more functional sub-sets of the integrated circuit.
In the test mode, which is normally activated upon reception by the TAP controller of a control signal for passage into the test mode, the controller produces a chaining control signal for the series connection of the latches of the configurable cells so as to form a shift register. This register comprises especially a serial input and a serial output respectively connected to an output and to an input of the TAP controller. The register also comprises a clock input for receiving a clock signal to set the pace of the flow of data circulating in the shift register.
In a first step, the TAP controller serially loads data into the latches of the configurable cells through the input of the shift register formed by these configurable cells. Then, the TAP controller changes the selection switching of the multiplexers to form the functional circuit and orders the execution of one or more cycles of the propagation signal by this functional circuit. In this phase, the data loaded into the latches of the configurable cells are processed by the functional circuit.
The controller then once again changes the selection switching of the multiplexers to again form the shift register and, at the output of the shift register, it serially retrieves the data stored in the latches of the configurable cells during the last cycle of the propagation signal. Despite the confirmed utility of this testing technique, its practical application may prove to be problematic in certain circumstances, especially in integrated circuits that process secret data.
Indeed, inasmuch as the activation of the test mode may enable a fraudulent individual to read the content of the latches of the configurable cells, this testing technique has the drawback of making such circuits highly vulnerable to fraudulent use. For example, by stopping a process of internal loading of secret data into the integrated circuit at various points in time and by unloading the contents of the shift register, a fraudulent person could obtain information on secret data, and even reconstruct this data.
By activating the test mode, a fraudulent individual could also obtain write access to the latches of the configurable cells to insert fraudulent data, or else place the integrated circuit in an unauthorized configuration. The fraudulent individual could thus, for example, access a register controlling a security element such as a sensor in order to deactivate it. Erroneous data could also be inserted to obtain information on secret data.
The fraudulent individual may in fact adopt two different strategies. The first strategy includes taking control of the TAP controller, and observing the contents of the cells of the shift register at the external pads. The second strategy includes taking control of the configurable cells by exciting them by micro-probing so as to simulate the driving of these cells by the command signals emitted by the TAP controller.
French application no. FR 05/07282 describes an electronic circuit designed to thwart an attempt at fraud. In '282 application, after entry into the test mode, an identifier of the user has to be input. If the identifier is correct, test data may be entered into the shift register. If not, an alert is activated and the circuit exits from the test mode. To this end, the electronic circuit comprises a detection circuit complementing the elements described above. This detection circuit is designed for the verification, if the chaining command signal is active, of the content of the shift register at the end of the period of time T1 needed for the input of the identifier into the register
According to the approach disclosed by the '282 application, the identifier has to be entered at each activation of the chaining command signal before data can be input into the shift register or output from this shift register. This soon becomes a constraint for test procedures of varying length during which the data has to be input or output several times. Furthermore, due to this difficulty, relatively short identifiers are used. They are faster to input into the register but also easier to find for a fraudulent person. Finally, since the identifier is input when the configurable cells are chained, the input of the identifier leads to the output of the initial content of the register which, as the case may be, may include the data to be protected from a fraudulent individual.